Integrated circuits and chips have become increasingly complex, with the speed and capacity of chips doubling about every eighteen months. This increase has resulted from advances in design software, fabrication technology, semiconductor materials, and chip design. The increased density of transistors per square centimeter and faster clock speeds, however, make it increasingly difficult to specify and design chips that perform as actually specified. Unanticipated and sometimes subtle interactions between the transistors and other electronic structures may adversely affect the performance of the circuit. These difficulties increase the expense and risk of designing and fabricating chips, especially those that are custom designed for a specific application. The demand for complex custom-designed chips increases with the burgeoning number and variety of applications and products controlled by microprocessors yet the time and money required to design chips have become a bottleneck in bringing these products to market. Without an assured successful outcome within a specified time, the risks have risen along with costs, and the result is that fewer organizations are willing to attempt the design and manufacture of custom chips.
Electronics are comprised of a myriad of semiconductor integrated circuits in complex arrangements intended to optimize the operation of the electronics. The integrated circuits may be arranged into blocks associated with a particular function. For instance, there may be several blocks involved in only the input/output (I/O) of signals to and from another block or group of blocks; there may be blocks of circuits and logic gates whose primary function is to store instantaneous state of the signals, such as registers and other memory units such as buffers, caches, etc.; there may be blocks having a primary purpose of manipulation of the signals using transistors, such as the logic gates and processors; there may be blocks whose only function may be the continuous monitoring and testing of the other blocks, etc. The parameters affecting the optimization of the operation of the integrated circuits, the chip as a whole, and each individual block are numerous and include, among other things, the functional features of the block, e.g., if the block is to be configured into memory, the size and number of ports of the memory, the location and configurability of the blocks together, the status of the blocks, the control logic of the blocks, the enabled features of the blocks, the type of testing of the blocks, the frequency and speed of the electrical signals traveling between and within the blocks; the interfaces between the blocks; the logic within the blocks, etc.
The design of integrated circuits and the placement of the blocks has been a tedious and specialized engineering task. Given a particular arrangement of the blocks on an integrated circuit, the more flexible a design, the more time it takes for a chip designer to modify and test any changes made to the design. For instance, an application-specific standard product (ASSP) such as off-the-shelf chips have no flexibility and yet the time to modify is short because another chip can be easily obtained from the shelf if another function is desired. Application specific integrated circuits (ASICs) increase in flexibility but are also more difficult to modify than standard products; just as metal layer programmable gate arrays (PGAs) are even more flexible in the numerous possible applications that can be achieved but more time-consuming to modify and test. Lastly, on the far end of the scale are field programmable gate arrays (FPGAs) that are very flexible and easy to modify but are very expensive and have a large die size.
Some fundamental anatomy of an integrated circuit will be helpful for a full understanding of the factors affecting the flexibility and difficulty in modifying designs. An integrated circuit is basically layers of a semiconductor, usually silicon, with specific areas and layers having different concentrations of electron and hole carriers and/or insulators. These specific areas and layers may interact with each other by field interactions or by direct electrical interconnections. These electrical interconnections may be within the semiconductor, or more usually, above the semiconductor areas and layers using a complex mesh of metal layers. Thus, with ASSPs and ASICs, all aspects of the integrated circuit are fixed, whereas with, e.g., PGAs and PFGAs, the interconnections and the logic can be programmed to achieve different functions. It is important to remember, however, that once the chip is manufactured, these parameters do not change and that reprogramming or modifying a feature is possible but difficult unless the chip has been specifically made for reprogramming.
A difficult optimization and construction problem of integrated circuits is that of constructing the various memory arrays required for any of the distinct designs. As a simplified example, a design for an integrated circuit might specify four memories, each 40 bits wide by 1024 words deep, organized as two-ported memory capable of a five nanosecond synchronous cycle time. But a customer specification may require three memories, the first of which may be 45 bits by 2048 words, have one port, and a cycle time of seven nanoseconds. The customer's second memory may be, e.g., 32 bits by 512 words, have two ports, and a cycle time of seven nanoseconds also. The third customer memory may be 32 bits by 512 words, have four ports with a cycle time of three nanoseconds.
Not only must the design engineer select and match gate arrays to create the required memory which is an extremely difficult optimization problem in itself, but the designer must also create the logic and other design views of these composed memories. This logic called register transfer logic (RTL) connects to the diffused memory and any generated memories from the logic array to create the required interface for compatibility of data width addressing, control, clock, and test, etc.
There is thus a need in the industry to increase the flexibility of the design process of the integrated circuits yet at the same time reduce the cost of each individual design.